The present invention relates to the suppression of cross diffusion and/or penetration in integrated circuit devices. More particularly, the present invention relates to a scheme for utilizing silicon rich barrier layers to suppress cross diffusion and penetration in memory cells and logic devices.
Integrated circuit devices commonly employ a laminar or polycilicide structure composed of a polysilicon film and an overlying film of a metal, metal silicide, or metal nitride. In many cases, the polysilicon film comprises an N+ polysilicon region doped with an N type impurity and a P+ polysilicon region doped with a P type impurity. The present inventors have recognized that many P+ and N+ dopant materials are subject to migration from a given polysilicon layer to another polysilicon layer, to an overlying conductive layer, or to another region of the given polysilicon layer. As a result, these opposite types of impurities are subject to cross diffusion. Additionally, the dopants may penetrate through a dielectric layer to dope the semiconductor substrate. This penetration may cause unwanted threshold voltage (Vt) shift in the semiconductor.
Accordingly, there is a need for a scheme for suppressing cross diffusion of dopant materials between oppositely doped regions of polysilicon layer and penetration of dopant material into the substrate in integrated circuit devices.